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This patch is built upon ppc-m4-macrology.patch. Using explicit register
names is working as expected now.

* aclocal.m4 (GMP_ASM_POWERPC_R_REGISTERS): New configure test,
adapted from corresponding test in GMP's acinlude.m4.
* configure.ac (ASM_PPC_WANT_R_REGISTERS): New substituted
variable. Set using GMP_ASM_POWERPC_R_REGISTERS, when powerpc64
assembly code is enabled.
* config.m4.in: Substituted here.
* powerpc64/machine.m4: Check ASM_PPC_WANT_R_REGISTERS, and
if needed, replace register names like r0, r1, ... with integers.
* Makefile.in (%.asm): Include m4-utils.m4 for preprocessing of .asm
files, and include config.m4 before machine.m4.

* m4-utils.m4: New file with m4 utilities, copied from GMP's
mpn/asm-defs.m4.
* Makefile.in (DISTFILES): Add m4-utils.m4.

Update powerpc64 files.

Update sparc files (32 and 64).

Update x86 files.

Update arm files.

Update shared m4 files and x86_64.

This patch adds "VSR" macro to improve the syntax of assembly code, I will
create a separate patch for gcm-hash since it hasn't merged yet to the
master. I also removed the TODO from README because I tried to use
"lxv/stxv" in POWER9 instead of  "lxvd2x/stxvd2x" but gcc produced
"lxvd2x/stxvd2x" in the binary. I'm not sure if it's variant issue of gcc
but this will be problematic since "lxvd2x/stxvd2x" need  permuting in
little-endian mode while "lxv/stxv" is endianness aware.

Based on patch by Mamone Tarsha.

Based on patch by Mamone Tarsha

I measured the latency and throughput of vcipher/vncipher/vxor instructions
for POWER8
vcipher/vncipher
throughput 6 instructions per cycle
latency 0.91 clock cycles
vxor
throughput 6 instructions per cycle
latency 0.32 clock cycles
So the ideal option for POWER8 is processing 8 blocks, it has +12%
performance over processing 4 blocks.