diff --git a/hw/Makefile b/hw/Makefile
index f32c554d6ab62d1b66ae9e2a864a39dbddc70531..dc67890e7b4543bf4a76edf7fc9f56c848a9a6aa 100644
--- a/hw/Makefile
+++ b/hw/Makefile
@@ -1,17 +1,12 @@
-IVERILOG_FLAGS = -g2005-sv -Wall
+IVERILOG_FLAGS = -g2005-sv -Wall -y arith/lib
 
 YOSYS_STATS = yosys -p "synth_ice40 $(STATS_FLAGS)" -f 'verilog -sv -DICE40'
 
-TARGETS = add-bk8-tb add-bk8s-tb add-h64-tb carry-64-tb \
-	genmask-tb mul3-stage-tb mul4-stage-tb mul6-stage-tb \
-	mul-3w64-tb mul-4w64-tb mul-6w64-tb \
-	ctz-tb reciprocal-tb srt-reciprocal-tb \
-	reg-file-tb reg-file-ice40-tb main
+TARGETS = main
 
 all: $(TARGETS)
 
-TESTS = add-bk8-tb add-bk8s-tb add-h64-tb carry-64-tb \
-	carry-only-tb \
+TESTS = add-h64-tb carry-64-tb carry-only-tb \
 	genmask-tb mul3-stage-tb mul4-stage-tb mul6-stage-tb ctz-tb \
 	mul-3w64-tb mul-4w64-tb mul-6w64-tb srt-reciprocal-tb reciprocal-tb \
 	reg-file-tb reg-file-ice40-tb shift-unit-tb alu-unit-tb popc-tb
@@ -20,43 +15,13 @@ check: all $(TESTS)
 	../run-tests $(TESTS)
 
 clean:
-	rm -f $(TARGETS)
+	rm -f $(TARGETS) $(TESTS)
 
 %: %.vl
-	iverilog $(IVERILOG_FLAGS) -o $@ $<
-
-add-bk8-tb: add-bk8.vl add-gp.vl
-add-bk8s-tb: add-bk8s.vl add-gp.vl
-add-h64-tb: add-h64.vl add-bk8.vl add-bk8s.vl add-gp.vl
-carry-64-tb: carry-64.vl add-gp.vl
-carry-only-tb: carry-only.vl add-gp.vl
-mul3-stage-tb: mul3-stage.vl
-mul4-stage-tb: mul4-stage.vl
-mul6-stage-tb: mul6-stage.vl
-mul-3w64-tb: add-gp.vl add-bk8.vl add-bk8s.vl \
-	add-h64.vl mul3-stage.vl mul-3w64.vl mul64-tb.vl
-mul-4w64-tb: add-gp.vl add-bk8.vl add-bk8s.vl \
-	add-h64.vl mul4-stage.vl mul-4w64.vl mul64-tb.vl
-mul-6w64-tb: add-gp.vl add-bk8.vl add-bk8s.vl \
-	add-h64.vl mul6-stage.vl mul-6w64.vl mul64-tb.vl
-
-# When re-enabling add_h64: add-gp.vl add-h64.vl
-srt-reciprocal-tb: add-bk8.vl add-bk8s.vl srt-reciprocal.vl
-
-genmask-tb: genmask.vl
-ctz-tb: ctz.vl
-popc-tb: popc.vl
-reciprocal-tb: reciprocal.vl
-reg-file-tb: reg-file.vl rf-tb.vl
-reg-file-ice40-tb: reg-file-ice40.vl rf-tb.vl
-shift-unit-tb: shift-unit.vl
-alu-unit-tb: alu-unit.vl
-
-main: reg-file.vl mem-mux.vl \
-	alu-unit.vl unary-unit.vl shift-unit.vl cnt-unit.vl \
-	mul-unit.vl reciprocal-unit.vl load-store-unit.vl \
-	instr-fetch.vl instr-decode.vl ctz.vl popc.vl srt-reciprocal.vl \
-	cpu.vl cpu-all.vl ram-unit.vl
+	iverilog $(IVERILOG_FLAGS) -Mall=$@.dT -o $@ $< \
+	&& sed 's,^,$@: ,' < $@.dT > $@.d && rm -f $@.dT
+
+-include $(TARGETS:=.d) $(TESTS:=.d)
 
 top-ice40-sim: top-ice40.vl cpu-all.vl reg-file-ice40.vl mem-mux.vl \
 	alu-unit.vl unary-unit.vl shift-unit.vl cnt-unit.vl \
diff --git a/hw/add-h64-tb.vl b/hw/add-h64-tb.vl
index 88d33ee811170a3a9934936b06030206b128931d..d8dbe6daf261bce2669da885968cd49aaddc70e1 100644
--- a/hw/add-h64-tb.vl
+++ b/hw/add-h64-tb.vl
@@ -15,9 +15,6 @@
 */
 
 `include "add-h64.vl"
-`include "add-bk8.vl"
-`include "add-bk8s.vl"
-`include "add-gp.vl"
 
 module main;
    reg [63:0] x;