diff --git a/assembler/keyword.h b/assembler/keyword.h
index 575f75f6bb73aafa41de6b5aa364e7b15afb9476..56eb5312562d119d9aef467860cee6ff2b3f5490 100644
--- a/assembler/keyword.h
+++ b/assembler/keyword.h
@@ -28,7 +28,7 @@
#define OPCODE_IMM_CMPUGT 0xc800
#define OPCODE_IMM_CMPSGT 0xc900
#define OPCODE_IMM_MOV 0xb000
-#define OPCODE_XOR 0xe500
+#define OPCODE_XOR 0xe300
#define OPCODE_MOV 0xe000
#define OPCODE_IMM_SIGN 0x0100
#define OPCODE_NOT 0xf910
diff --git a/assembler/keyword.in b/assembler/keyword.in
index 070017b0d3d482b2c50c902be42e073c7a8329f8..7570a113905836a26c8e7ef4f70c7bcdbb70250e 100644
--- a/assembler/keyword.in
+++ b/assembler/keyword.in
@@ -77,8 +77,8 @@ rot32, KEYWORD_ROT32, TOK_INSTR_SHIFT, 0x6c01, 0
# for a binary operation.
jmp, KEYWORD_JMP, TOK_INSTR_BRANCH, 0x8000, 0xe001
jsr, KEYWORD_JSR, TOK_INSTR_BRANCH, 0x8400, 0xf940
-bt, KEYWORD_BT, TOK_INSTR_BRANCH, 0x8800, 0xe101
-bf, KEYWORD_BF, TOK_INSTR_BRANCH, 0x8c00, 0xe201
+bt, KEYWORD_BT, TOK_INSTR_BRANCH, 0x8800, 0xe401
+bf, KEYWORD_BF, TOK_INSTR_BRANCH, 0x8c00, 0xe501
bnz, KEYWORD_BNZ, TOK_INSTR_BRANCH, 0x9000, 0
# Floating point ops missing.
#
@@ -100,11 +100,11 @@ sub8, KEYWORD_SUB8, TOK_INSTR_BINARY, 0xd806, 0
sub16, KEYWORD_SUB16, TOK_INSTR_BINARY, 0xd804, 0
sub32, KEYWORD_SUB32, TOK_INSTR_BINARY, 0xd802, 0
mov, KEYWORD_MOV, TOK_INSTR_BINARY, 0xe000, 0xb001
-movt, KEYWORD_MOVT, TOK_INSTR_BINARY, 0xe100, 0
-movf, KEYWORD_MOVF, TOK_INSTR_BINARY, 0xe200, 0
-and, KEYWORD_AND, TOK_INSTR_BINARY, 0xe300, 0xb200
-or, KEYWORD_OR, TOK_INSTR_BINARY, 0xe400, 0xb400
-xor, KEYWORD_XOR, TOK_INSTR_BINARY, 0xe500, 0xb600
+and, KEYWORD_AND, TOK_INSTR_BINARY, 0xe100, 0xb200
+or, KEYWORD_OR, TOK_INSTR_BINARY, 0xe200, 0xb400
+xor, KEYWORD_XOR, TOK_INSTR_BINARY, OPCODE_XOR, 0xb600
+movt, KEYWORD_MOVT, TOK_INSTR_BINARY, 0xe400, 0
+movf, KEYWORD_MOVF, TOK_INSTR_BINARY, 0xe500, 0
mullo, KEYWORD_MULLO, TOK_INSTR_BINARY, 0xe600, 0
umulhi, KEYWORD_UMULHI, TOK_INSTR_BINARY, 0xe700, 0
shift, KEYWORD_SHIFT, TOK_INSTR_BINARY, 0xe800, 0
diff --git a/hw/cpu/lib/instr_decode.v b/hw/cpu/lib/instr_decode.v
index 21da843991cacbdee3d19f83af5cb19f976a6b03..e132cd61ab9c5dc04804eafb281dbeb0d1815a2b 100644
--- a/hw/cpu/lib/instr_decode.v
+++ b/hw/cpu/lib/instr_decode.v
@@ -447,38 +447,31 @@ module instr_decode (input [15:0] instr,
dst_mode = 2'b00;
dst_write_enable = 1;
end
- /* Mov if true */
- 'b11100001????????: begin
- alu_enable = 1;
- alu_op = `OP_ALU_MOVC;
- op_cin = 2'b10;
- dst_write_enable = 1;
- end
- /* Mov if false */
- 'b11100010????????: begin
- alu_enable = 1;
- alu_op = `OP_ALU_MOVC;
- op_cin = 2'b11;
- dst_write_enable = 1;
- end
/* And */
- 'b11100011????????: begin
+ 'b11100001????????: begin
alu_enable = 1;
alu_op = `OP_ALU_AND;
dst_write_enable = 1;
end
/* Or */
- 'b11100100????????: begin
+ 'b11100010????????: begin
alu_enable = 1;
alu_op = `OP_ALU_OR;
dst_write_enable = 1;
end
/* Xor */
- 'b11100101????????: begin
+ 'b11100011????????: begin
alu_enable = 1;
alu_op = `OP_ALU_XOR;
dst_write_enable = 1;
end
+ /* Movt/movf */
+ 'b1110010?????????: begin
+ alu_enable = 1;
+ alu_op = `OP_ALU_MOVC;
+ op_cin = {1'b1, instr[8]};
+ dst_write_enable = 1;
+ end
/* Mullo/mulhi */
'b1110011?????????: begin
mul_enable = 1;
diff --git a/instr16.tex b/instr16.tex
index 76ea5a4a718a4d60efbea2a134e7552323f700c0..77f39234c8e9e7cf95750b6e2a946047c07068ab 100644
--- a/instr16.tex
+++ b/instr16.tex
@@ -676,11 +676,11 @@ messy.
1101 \> 1ioo \> $s$ \> $d$ \> sub \> $r_d$, $r_s$ \>
Subtract, carry handling as above \\
1110 \> 0000 \> $s$ \> $d$ \> mov \> $r_d$, $r_s$ \\
- 1110 \> 0001 \> $s$ \> $d$ \> movt \> $r_d$, $r_s$ \> Move if flag set \\
- 1110 \> 0010 \> $s$ \> $d$ \> movf \> $r_d$, $r_s$ \> Move if flag clear \\
- 1110 \> 0011 \> $s$ \> $d$ \> and \> $r_d$, $r_s$ \\
- 1110 \> 0100 \> $s$ \> $d$ \> or \> $r_d$, $r_s$ \\
- 1110 \> 0101 \> $s$ \> $d$ \> xor \> $r_d$, $r_s$ \\
+ 1110 \> 0001 \> $s$ \> $d$ \> and \> $r_d$, $r_s$ \\
+ 1110 \> 0010 \> $s$ \> $d$ \> or \> $r_d$, $r_s$ \\
+ 1110 \> 0011 \> $s$ \> $d$ \> xor \> $r_d$, $r_s$ \\
+ 1110 \> 0100 \> $s$ \> $d$ \> movt \> $r_d$, $r_s$ \> Move if flag set \\
+ 1110 \> 0101 \> $s$ \> $d$ \> movf \> $r_d$, $r_s$ \> Move if flag clear \\
1110 \> 0110 \> $s$ \> $d$ \> mullo \> $r_d$, $r_s$ \> $r_d \gets
r_d r_s \bmod 2^\ell$ \\
1110 \> 0111 \> $s$ \> $d$ \> umulhi \> $r_d$, $r_s$ \>
diff --git a/simulator/cpu.c b/simulator/cpu.c
index d5ec81f6cc0e14ae332506391930d7bb741abaad..da7da222c5025f804e382537b5bf5bdb5975f634 100644
--- a/simulator/cpu.c
+++ b/simulator/cpu.c
@@ -775,23 +775,23 @@ i_binary_op (struct cpu *cpu, struct memory *memory, uint16_t instr)
case 0: /* mov */
CPUW (dreg, s);
break;
- case 1: /* movt */
- if (cpu->cc_flag)
- CPUW (dreg, s);
- break;
- case 2: /* movf */
- if (!cpu->cc_flag)
- CPUW (dreg, s);
- break;
- case 3: /* and */
+ case 1: /* and */
CPUW (dreg, d & s);
break;
- case 4: /* or */
+ case 2: /* or */
CPUW (dreg, d | s);
break;
- case 5: /* xor */
+ case 3: /* xor */
CPUW (dreg, d ^ s);
break;
+ case 4: /* movt */
+ if (cpu->cc_flag)
+ CPUW (dreg, s);
+ break;
+ case 5: /* movf */
+ if (!cpu->cc_flag)
+ CPUW (dreg, s);
+ break;
case 6: /* mullo */
CPUW (dreg, d * s);
break;
diff --git a/testsuite/as-imm-test b/testsuite/as-imm-test
index a5d7742df4b600d4dd84fc3dc54823cf2aedee2e..5b9de09916fd66074de37a16b143407e75baba67 100755
--- a/testsuite/as-imm-test
+++ b/testsuite/as-imm-test
@@ -2,8 +2,8 @@
. ./functions.sh
-test_as "e5 33" "and r3, #0"
-test_as "e5 33" "and r3, #0x"
+test_as "e3 33" "and r3, #0"
+test_as "e3 33" "and r3, #0x"
test_as "b2 13" "and r3, #1"
test_as "b2 23" "and r3, #2"
test_as "b2 33" "and r3, #3"
diff --git a/testsuite/as-regops-test b/testsuite/as-regops-test
index 85edef4dca35f88ed3f1b3d9ae2516056d350e34..bff13b1d2b284ef724874aee9eeaa24958129b80 100755
--- a/testsuite/as-regops-test
+++ b/testsuite/as-regops-test
@@ -22,11 +22,11 @@ test_as "dd fe" "subc r14, cc, r15"
test_as "de 10" "subs r0, cc, r1"
test_as "df 21" "subv r1, cc, r2"
test_as "e0 10" "mov r0, r1"
-test_as "e1 21" "movt r1, r2"
-test_as "e2 32" "movf r2, r3"
-test_as "e3 43" "and r3, r4"
-test_as "e4 54" "or r4, r5"
-test_as "e5 65" "xor r5, r6"
+test_as "e1 43" "and r3, r4"
+test_as "e2 54" "or r4, r5"
+test_as "e3 65" "xor r5, r6"
+test_as "e4 21" "movt r1, r2"
+test_as "e5 32" "movf r2, r3"
test_as "e6 76" "mullo r6, r7"
test_as "e7 87" "umulhi r7, r8"
test_as "e8 98" "shift r8, r9"