Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
N
nettle
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Package registry
Container registry
Model registry
Operate
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Norbert Pócs
nettle
Commits
8c4ef180
Commit
8c4ef180
authored
Jun 25, 2020
by
Niels Möller
Browse files
Options
Downloads
Patches
Plain Diff
arm: Micro optimize neon implementation of salsa20 and chacha
parent
db9b66e0
No related branches found
No related tags found
No related merge requests found
Changes
3
Show whitespace changes
Inline
Side-by-side
Showing
3 changed files
ChangeLog
+5
-0
5 additions, 0 deletions
ChangeLog
arm/neon/chacha-core-internal.asm
+12
-16
12 additions, 16 deletions
arm/neon/chacha-core-internal.asm
arm/neon/salsa20-core-internal.asm
+4
-8
4 additions, 8 deletions
arm/neon/salsa20-core-internal.asm
with
21 additions
and
24 deletions
ChangeLog
+
5
−
0
View file @
8c4ef180
2020-06-25 Niels Möller <nisse@lysator.liu.se>
2020-06-25 Niels Möller <nisse@lysator.liu.se>
* arm/neon/chacha-core-internal.asm (QROUND): Micro optimize
rotations, using the vsra.u32 instruction. Gives 10% speedup,
benchmarked on Cortex-A5. Suggested by Torbjörn Granlund.
* arm/neon/salsa20-core-internal.asm (QROUND): Likewise.
* x86_64/chacha-core-internal.asm (QROUND): Fix use of macro
* x86_64/chacha-core-internal.asm (QROUND): Fix use of macro
arguments. Spotted by Torbjörn Granlund.
arguments. Spotted by Torbjörn Granlund.
...
...
This diff is collapsed.
Click to expand it.
arm/neon/chacha-core-internal.asm
+
12
−
16
View file @
8c4ef180
...
@@ -54,28 +54,24 @@ define(<QROUND>, <
...
@@ -54,28 +54,24 @@ define(<QROUND>, <
C
x2
+
=
x3
,
x1
^
=
x2
,
x1
lrot
7
C
x2
+
=
x3
,
x1
^
=
x2
,
x1
lrot
7
vadd.i32
$
1
,
$
1
,
$
2
vadd.i32
$
1
,
$
1
,
$
2
veor
$
4
,
$
4
,
$
1
veor
T0
,
$
4
,
$
1
vshl.i32
T0
,
$
4
,
#
16
vshl.i32
$
4
,
T0
,
#
16
vshr.u32
$
4
,
$
4
,
#
16
vsra.u32
$
4
,
T0
,
#
16
veor
$
4
,
$
4
,
T0
vadd.i32
$
3
,
$
3
,
$
4
vadd.i32
$
3
,
$
3
,
$
4
veor
$
2
,
$
2
,
$
3
veor
T0
,
$
2
,
$
3
vshl.i32
T0
,
$
2
,
#
12
vshl.i32
$
2
,
T0
,
#
12
vshr.u32
$
2
,
$
2
,
#
20
vsra.u32
$
2
,
T0
,
#
20
veor
$
2
,
$
2
,
T0
vadd.i32
$
1
,
$
1
,
$
2
vadd.i32
$
1
,
$
1
,
$
2
veor
$
4
,
$
4
,
$
1
veor
T0
,
$
4
,
$
1
vshl.i32
T0
,
$
4
,
#
8
vshl.i32
$
4
,
T0
,
#
8
vshr.u32
$
4
,
$
4
,
#
24
vsra.u32
$
4
,
T0
,
#
24
veor
$
4
,
$
4
,
T0
vadd.i32
$
3
,
$
3
,
$
4
vadd.i32
$
3
,
$
3
,
$
4
veor
$
2
,
$
2
,
$
3
veor
T0
,
$
2
,
$
3
vshl.i32
T0
,
$
2
,
#
7
vshl.i32
$
2
,
T0
,
#
7
vshr.u32
$
2
,
$
2
,
#
25
vsra.u32
$
2
,
T0
,
#
25
veor
$
2
,
$
2
,
T0
>
)
>
)
.text
.text
...
...
This diff is collapsed.
Click to expand it.
arm/neon/salsa20-core-internal.asm
+
4
−
8
View file @
8c4ef180
...
@@ -53,26 +53,22 @@ define(<S3>, <q15>)
...
@@ -53,26 +53,22 @@ define(<S3>, <q15>)
define
(
<
QROUND
>
,
<
define
(
<
QROUND
>
,
<
vadd.i32
T0
,
$
1
,
$
4
vadd.i32
T0
,
$
1
,
$
4
vshl.i32
T1
,
T0
,
#
7
vshl.i32
T1
,
T0
,
#
7
vshr.u32
T0
,
T0
,
#
25
vsra.u32
T1
,
T0
,
#
25
veor
$
2
,
$
2
,
T0
veor
$
2
,
$
2
,
T1
veor
$
2
,
$
2
,
T1
vadd.i32
T0
,
$
1
,
$
2
vadd.i32
T0
,
$
1
,
$
2
vshl.i32
T1
,
T0
,
#
9
vshl.i32
T1
,
T0
,
#
9
vshr.u32
T0
,
T0
,
#
23
vsra.u32
T1
,
T0
,
#
23
veor
$
3
,
$
3
,
T0
veor
$
3
,
$
3
,
T1
veor
$
3
,
$
3
,
T1
vadd.i32
T0
,
$
2
,
$
3
vadd.i32
T0
,
$
2
,
$
3
vshl.i32
T1
,
T0
,
#
13
vshl.i32
T1
,
T0
,
#
13
vshr.u32
T0
,
T0
,
#
19
vsra.u32
T1
,
T0
,
#
19
veor
$
4
,
$
4
,
T0
veor
$
4
,
$
4
,
T1
veor
$
4
,
$
4
,
T1
vadd.i32
T0
,
$
3
,
$
4
vadd.i32
T0
,
$
3
,
$
4
vshl.i32
T1
,
T0
,
#
18
vshl.i32
T1
,
T0
,
#
18
vshr.u32
T0
,
T0
,
#
14
vsra.u32
T1
,
T0
,
#
14
veor
$
1
,
$
1
,
T0
veor
$
1
,
$
1
,
T1
veor
$
1
,
$
1
,
T1
>
)
>
)
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment