Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
N
nettle
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Container registry
Model registry
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
GitLab community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Wim Lewis
nettle
Commits
084733ae
Commit
084733ae
authored
Mar 14, 2013
by
Niels Möller
Browse files
Options
Downloads
Patches
Plain Diff
Use neon registers for loading the input. Slight slowdown.
parent
45040019
No related branches found
No related tags found
No related merge requests found
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
armv7/sha512-compress.asm
+33
-27
33 additions, 27 deletions
armv7/sha512-compress.asm
with
33 additions
and
27 deletions
armv7/sha512-compress.asm
+
33
−
27
View file @
084733ae
...
@@ -142,37 +142,43 @@ PROLOGUE(_nettle_sha512_compress)
...
@@ -142,37 +142,43 @@ PROLOGUE(_nettle_sha512_compress)
push
{
r4
,
r5
,
r6
,
r7
,
r8
,
r10
,
r14
}
push
{
r4
,
r5
,
r6
,
r7
,
r8
,
r10
,
r14
}
sub
sp
,
sp
,
#
128
sub
sp
,
sp
,
#
128
C
Load
data
up
front.
FIXME
:
Use
al
igned
vld1
,
and
vshl.
ands
SHIFT
,
INPUT
,
#
7
and
INPUT
,
INPUT
,
#
-
8
ands
SHIFT
,
INPUT
,
#
3
vld1.8
{
d0
}
,
[
INPUT
:
64
]
and
INPUT
,
INPUT
,
$
-
4
addne
INPUT
,
INPUT
,
#
8
addeq
SHIFT
,
SHIFT
,
#
8
lsl
SHIFT
,
SHIFT
,
#
3
lsl
SHIFT
,
SHIFT
,
#
3
mov
I0
,
#
0
movne
I0
,
#
-
1
C
Put
right
shift
in
d2
and
d3
,
aka
q1
lsl
I1
,
I0
,
SHIFT
neg
SHIFT
,
SHIFT
uadd8
I0
,
I0
,
I1
C
Sets
APSR.GE
bits
vmov.i32
d2
,
#
0
ldr
I0
,
[
INPUT
]
vmov.32
d2
[
0
],
SHIFT
addne
INPUT
,
INPUT
,
#
4
vmov
d3
,
d2
C
Put
left
shift
in
d4
and
d5
,
aka
q2
add
SHIFT
,
SHIFT
,
#
64
vmov.i32
d4
,
#
0
vmov.32
d4
[
0
],
SHIFT
vmov
d5
,
d4
vshl.u64
d0
,
d0
,
d2
mov
DS
T
,
sp
mov
DS
T
,
sp
mov
COUNT
,
#
8
mov
COUNT
,
#
4
.Lcopy:
.Lcopy:
ldm
INPUT
!
,
{
I1
,
I2
,
I3
,
I4
}
C
Set
w
[
i
]
<--
w
[
i
-
1
]
>>
RSHIFT
+
w
[
i
]
<<
LSHIFT
sel
IT
,
I0
,
I1
vld1.8
{
d16
,
d17
,
d18
,
d19
}
,
[
INPUT
:
64
]
!
ror
IT
,
IT
,
SHIFT
vshl.u64
q3
,
q8
,
q1
C
Right
shift
sel
I0
,
I1
,
I2
vshl.u64
q8
,
q8
,
q2
C
Left
shift
ror
I0
,
I0
,
SHIFT
veor
d16
,
d16
,
d0
rev
I0
,
I0
veor
d17
,
d17
,
d6
rev
I1
,
IT
vrev64.8
q8
,
q8
sel
IT
,
I2
,
I3
vshl.u64
q0
,
q9
,
q1
C
Right
shift
ror
IT
,
IT
,
SHIFT
vshl.u64
q9
,
q9
,
q2
C
Left
shift
sel
I2
,
I3
,
I4
veor
d18
,
d18
,
d7
ror
I2
,
I2
,
SHIFT
veor
d19
,
d19
,
d0
rev
I2
,
I2
vrev64.8
q9
,
q9
rev
I3
,
IT
subs
COUNT
,
COUNT
,
#
1
subs
COUNT
,
COUNT
,
#
1
st
m
DS
T
!
,
{
I0
,
I1
,
I2
,
I3
}
v
st
1.64
{
d16
,
d17
,
d18
,
d19
}
,
[
DS
T
]
!
mov
I
0
,
I4
v
mov
d
0
,
d1
bne
.Lcopy
bne
.Lcopy
mov
COUNT
,
#
2
mov
COUNT
,
#
2
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment