Use add_h64 and carry_64 in srt_reciprocal.

hw/Makefile

@@ -39,7 +39,7 @@ mul-6w64-tb: add-gp.vl add-bk8.vl add-bk8s.vl \
 	add-h64.vl mul6-stage.vl mul-6w64.vl mul64-tb.vl
 
 # When re-enabling add_h64: add-gp.vl add-h64.vl
-srt-reciprocal-tb: add-bk8.vl add-bk8s.vl srt-reciprocal.vl
+srt-reciprocal-tb: add-bk8.vl add-bk8s.vl carry-64.vl srt-reciprocal.vl
 
 genmask-tb: genmask.vl
 ctz-tb: ctz.vl

hw/cpu-all.vl

@@ -36,9 +36,10 @@
 `include "instr-fetch.vl"
 `include "ctz.vl"
 `include "popc.vl"
-`include "srt-reciprocal.vl"
 `include "add-gp.vl"
 `include "add-bk8.vl"
 `include "add-bk8s.vl"
 `include "add-h64.vl"
+`include "carry-64.vl"
+`include "srt-reciprocal.vl"
 `include "cpu.vl"

hw/srt-reciprocal-tb.vl

@@ -18,6 +18,7 @@
 `include "add-bk8.vl"
 `include "add-bk8s.vl"
 `include "add-h64.vl"
+`include "carry-64.vl"
 `include "srt-reciprocal.vl"
 
 module main;

hw/srt-reciprocal.vl

@@ -73,8 +73,8 @@ module srt_final_q (input [2*n-1:0] q, input adjust, output [n-1:0] out);
       end
    endgenerate
 
-   assign out = q_pos + q_neg + !adjust;
-   // add_h64 add (q_pos, q_neg, !adjust, {dummy, out});
+   // assign out = q_pos + q_neg + !adjust;
+   add_h64 add (q_pos, q_neg, !adjust, {dummy, out});
 endmodule // srt_final_q
 
 // NOTE: Requires d input to be kept stable, in reciprocal_unit it is
@@ -94,7 +94,7 @@ module srt_reciprocal(input clk, input rst, input enable,
    wire [1:0]	q;
    wire [n:0]	s;
    wire [n-3:2] c;
-   wire [n:1]	p;
+   wire 	carry;
 
    always @(posedge clk) begin
       if (rst) begin
@@ -123,12 +123,9 @@ module srt_reciprocal(input clk, input rst, input enable,
    srt_qsel qsel(s_reg[n:n-3], q);
    srt_update #(n) update({s_reg[n-1:0], 1'b1}, c_reg, d, q, s, c);
 
-   /* FIXME: Only need sign bit from this addition. Should be arranged
-      so we get the resulting sign from a Kogge-Stone tree, in
-      parallel with most of the addition work to construct q, with
-      only final carry-select logic remaining when the sign is ready.
-    */
-   assign p = s_reg[n:1] + {3'b0, c_reg};
+   /* Only need sign bit from this addition */
+   carry_64 carry_adjust({s_reg[n-1:1], 1'b0}, {3'b0, c_reg, 1'b0}, 1'b0, carry);
 
-   srt_final_q #(n) final_q (q_reg, p[n], q_out);
+   /* Construct sign as carry ^ s_reg[n] */
+   srt_final_q #(n) final_q (q_reg, carry ^ s_reg[n], q_out);
 endmodule // srt_reciprocal